Within the last several years, computer chip makers have steadily been increasing the number of computer cores that enable operations to be run simultaneously instead of sequentially. At the same time, PC-based Windows operating systems have mostly transitioned from 32-bit computing platforms to 64-bit platforms, permitting the use of vast amounts of a workstation’s physical memory. Both technologies have the potential to dramatically improve transport model computing performance. Unfortunately, in many cases, large scale programming changes are necessary to take advantage of these technologies, and as a result, many transportation models do not yet fully exploit all available processing power and memory.

This presentation details research, development, and application of transportation models that fully utilize multi-core processing and 64-bit programming. For multi-core processing, the presentation details the transformation of common transport models such as network skimming, assignment, logit evaluation, and matrix operations from sequential single core to multi-threaded simultaneous processing. For 64-bit programming, the presentation analyzes transport models that utilize large amounts of memory. Examples of such models are matrix operations, path-based network assignments, and multi-class equilibrium-based transit assignments. This presentation also details the research and results of combining these optimization strategies, such as running multiple multi-core operations in parallel or on different computers. Lastly, this presentation describes possible user interfaces and programming pseudo-code for users and model developers to understand, set up, and implement these multi-core, parallel, and high-memory strategies.

This presentation documents the performance of these models on large scale datasets from New York City, Los Angeles, Washington D.C. and other large metropolitan areas in the United States. We will present examples and compare procedure run times, CPU utilization, and memory and other computer hardware requirements for each optimization strategy. The presentation also details auxiliary issues encountered during development and implementation such as computer and algorithm limitations.